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 2. 196À» ¹è¿öº¸ÀÚ

 

4. 196KCÀÇ IO port

 

4-1. 80C196KCÀÇ SFR

¾Õ¿¡¼­µµ ÀÌ¹Ì SFR¿¡ ´ëÇØ ¾ð±ÞÇßÁö¸¸, ¿©±â¿¡¼­ ´Ù½Ã ¾ð±ÞÇϵµ·Ï ÇÑ´Ù.

¸ðµç IO port´Â SFRÀ» ÅëÇؼ­ Á¦¾îÇÑ´Ù. port3°ú 4¸¦ Á¦¿ÜÇÑ 80C196KCÀÇ ÁÖº¯ ÀåÄ¡´Â ¸ðµÎ SFRÀ» ÀÌ¿ëÇÏ¿© Á¦¾îÇÒ ¼ö°¡ ÀÖ´Ù. ÇÑÆí SFRÀ» accessÇϴµ¥ ÀÖ¾î ¼öÆò window¸¦ Àß ÀÌÇØÇØ¾ß ÇÑ´Ù. ´Ù½Ã ´ÙÀ½ Ç¥¸¦ Âü°íÇϵµ·Ï ÇÑ´Ù. ¾Æ·¡ Ç¥¿¡¼­ À½¿µºÎºÐÀº 196KCÀÇ IO port¸¦ Á¦¾îÇϱâ À§ÇÑ SFRµéÀÌ´Ù.

address

¼öÆò window 0

Read

¼öÆò window 0

Write

¼öÆò window 1

Read/Write

¼öÆò window 15

Read

¼öÆò window 15

Write

17H

IOS2

PWMO_CONTROL

PWM2_CONTROL

PWM0_CONTROL

IOS2

16H

IOS1

IOC1

PWM1_CONTROL

IOC1

IOS1

15H

IOS0

IOC0

reserved**

IOC0

IOS0

14H

WSR

WSR

WSR

WSR

WSR

13H

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

INT_MASK1

12H

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

INT_PEND1

11H

SP_STAT

SP_CON

reserved**

SP_CON

SP_STAT

10H

PORT2

PORT2

reserved**

reserved**

reserved**

0FH

PORT1

PORT1

reserved**

reserved**

reserved**

0EH

PORT0

BAUD_RATE

reserved**

reserved**

reserved**

0DH

TIMER2(HI)

TIMER2(HI)

reserved**

T2CAPTURE(HI)

T2CAPTURE(HI)

0CH

TIMER2(LO)

TIMER1(LO)

IOC3

T2CAPTURE(LO)

T2CAPTURE(LO)

0BH

TIMER1(HI)

IOC2

reserved**

IOC2

TIMER1(HI)

0AH

TIMER1(LO)

WATCHDOG

reserved**

WATCHDOG

TIMER1(LO)

09H

INT_PEND

INT_PEND

INT_PEND

INT_PEND

INT_PEND

08H

INT_MASK

INT_MASK

INT_MASK

INT_MASK

INT_MASK

07H

SBUF(Rx)

SBUF(Tx)

PTSSRV(HI)

SBUF(Tx)

SBUF(Rx)

06H

HSI_STATUS

HSO_COMMAND

PTSSRV(LO)

HSO_COMMAND

HSI_STATUS

05H

HSI_TIME(HI)

HSO_TIME(HI)

PTSSEL(HI)

HSO_TIME(HI)

HSI_TIME(HI)

04H

HSI_TIME(LO)

HSO_TIME(LO)

PTSSEL(LO)

HSO_TIME(LO)

HSI_TIME(LO)

03H

AD_RESULT(HI)

HSI_MODE

AD_TIME

HSI_MODE

AD_RESULT(HI)

02H

AD_RESULT(LO)

AD_COMMAND

reserved**

AD_COMMAND

AD_RESULT(LO)

01H

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

ZERO_REG(HI)

00H

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

ZERO_REG(LO)

** reserved byte´Â 0À¸·Î ½áÁø´Ù.

¿©±â¼­ ´ÙÀ½ ¿¹¸¦ »ìÆ캸ÀÚ.

ANDB IOS2, 50H

ÀÌ´Â IOS2ÀÇ ³»¿ë°ú 50HÀÇ ³»¿ëÀ» ANDÇÏ¿© IOS2¿¡ ÀúÀåÇϱâ À§ÇÑ ÇÁ·Î±×·¥ÀÌ´Ù. ±×·¯³ª ÀÌ´Â À߸øµÈ °ÍÀÌ´Ù. IOS2¿Í 50H¸¦ Çϱâ À§Çؼ­´Â ¸ÕÀú 50H¿Í IOS2ÀÇ ³»¿ëÀ» Àоî¾ß Çϴµ¥, ¿©±â¿¡¼­ IOS2ÀÇ ³»¿ëÀ» ÀаԵǸé(ÇöÀç WSR=0À̶ó°í °¡Á¤, default) IOS2ÀÇ ³»¿ëÀÌ ÀÐÇôÁö°Ô µÇ¹Ç·Î ÀÌ»óÀÌ ¾øÀ» °ÍÀÌ´Ù. ±×·¯³ª À̸¦ ´Ù½Ã IOS2¿¡ ¾²°Ô µÇ¸é, À̶§¿¡´Â IOS2¿¡ ¾²¿©Áö´Â °ÍÀÌ ¾Æ´Ï¶ó, PWM0_CONTROL¿¡ ¾²¿©Áö°Ô µÈ´Ù. µû¶ó¼­ ¿¹»óÄ¡ ¸øÇÑ °á°ú°¡ »ý±æ °ÍÀÌ´Ù. µû¶ó¼­ ÀÌ ÇÁ·Î±×·¥Àº ´ÙÀ½°ú °°ÀÌ °íÃÄ¾ß ÇÑ´Ù.

LDB 40H, IOS2 ; 40H´Â Àӽà register

ANDB 40H, 50H

LDB WSR, #15 ; IOS2¿¡ ¾²±â À§Çؼ­ ¼öÆò window 15 ¼±ÅÃ

LDB IOS2, 40H

CLRB WSR ; ¼öÆò window º¹±Í

ÀÌ ³»¿ëÀº ¾Õ¼­ ÀÌ¹Ì ¾ð±ÞÇßÁö¸¸, Áß¿äÇϱ⠶§¹®¿¡ ´Ù½Ã ¾ð±ÞÇÑ´Ù. ¾ÕÀ¸·Î´Â SFR¿¡ ´ëÇÑ ³»¿ëÀº ¾ð±ÞÇÏÁö ¾ÊÀ» °ÍÀÌ´Ù.

´ÙÀ½Àº 196KCÀÇ SFRÀÇ ±â´ÉÀ» ¿ä¾àÇÑ °ÍÀÌ´Ù. SFRÀÇ ±â´É¿¡ ´ëÇÑ ³»¿ëÀÌ Ã³À½ ³ª¿À°Ô µÇ¹Ç·Î ¿©±â¿¡¼­´Â ¸ðµç SFRÀÇ ±â´É¿¡ ´ëÇØ ¼³¸íÇÏÁö¸¸, ÀÌÁ¦ºÎÅÍ´Â °¢°¢ÀÇ device¿¡ ÇÊ¿äÇÑ SFR¸¸À» ¼³¸íÇÏ°Ô µÉ °ÍÀÌ´Ù.

register

±â´É

ZERO_REG

Zero register·Î Ç×»ó 0000H°¡ ÀúÀåµÇ¾î ÀÖ´Ù.

AD_RESULT

A/D º¯È¯ °á°ú ¹× A/D converterÀÇ »óÅ°¡ ÀúÀåµÈ´Ù.

AD_COMMAND

A/D converter¸¦ Á¦¾îÇÑ´Ù.

HSI_MODE

HSI(High Speed Input)ÀÇ trigger pulseÀÇ mode¸¦ °áÁ¤ÇÑ´Ù.

HSI_TIME

HSI°¡ triggerµÈ ¼ø°£¿¡ timer1ÀÇ °ªÀÌ ÀúÀåµÈ´Ù.

HSO_COMMAND

HSO(High Speed Output)¸¦ Á¦¾îÇÑ´Ù.

HSI_STATUS

HSIÀÇ pin »óÅ°¡ ÀúÀåµÈ´Ù.

SBUF(TX)

transmit buffer for serial port

SBUF(RX)

receive buffer for serial port

INT_MASK

interrupt mask register, ÇØ´ç bit¿¡ 0/1À» ¾²¸é interrupt disable/enable

INT_PEND

interrupt ½ÅÈ£ÀÇ ÀÔ·Â »óŸ¦ Ç¥½ÃÇÑ´Ù.

WATCHDOG

64KÀÇ state ½Ã°£ µî¿¡¼­ CPU resetÀÌ °É¸®´Â ½Ã°£À» ȸÇÇÇÑ´Ù.

TIMER1

Timer1ÀÇ ½ÃÁ¤¼ö¸¦ ÀúÀåÇÑ´Ù.

TIMER2

Timer2ÀÇ ½ÃÁ¤¼ö¸¦ ÀúÀåÇÑ´Ù.

PORT0

port0ÀÇ digital ÀÔ·Â ½ÅÈ£¸¦ ÀúÀåÇÑ´Ù.

BAUD_RATE

serial portÀÇ ¼Û/¼ö½Å baud rate¸¦ ¼³Á¤ÇÑ´Ù.

PORT1

port1ÀÇ ÀÔ/Ãâ·Â register

PORT2

port2ÀÇ ÀÔ/Ãâ·Â register

SP_STAT

serial port status register

SP_CON

serial port control register

IOS0

IO status register 0

IOS1

IO status register 1

IOS2

IO status register 2

IOC0

IO control register 0

IOC1

IO control register 1

IOC2

IO control register 2

IOC3

IO control register 3

PWM_CONTROL

PWM(Pulse Width Modulation)ÀÇ counter. PWMÀÇ pulth width¸¦ Á¦¾îÇÑ´Ù.

INT_PEND1

interrupt pending register 1 (196KCÀÇ »óÀ§ 8°³ interrupt)

INT_MASK1

interrupt mask register 1

WSR

Window Select Register

4-2. IO control register¿Í status register

 

IOC0   (15H HWIN 0 write)

          (15H HWIN 15 read)

0

HSI.0 input enable/

1

Timer2 reset each write

2

HSI.1 input enable/

3

Timer2 external reset each write

4

HSI.2 input enable/

5

Timer2 reset source HSI.0/

6

HSI.3 input enable/

7

Timer2 clock source HSI.1/

IOS0   (15H HWIN 0 read)

          (15H HWIN 15 write)

0

HSO.0 ÇöÀç»óÅÂ

1

HSO.1 ÇöÀç»óÅÂ

2

HSO.2 ÇöÀç»óÅÂ

3

HSO.3 ÇöÀç»óÅÂ

4

HSO.4 ÇöÀç»óÅÂ

5

HSO.5 ÇöÀç»óÅÂ

6

CAM or holding register full

7

HSO holding register full

IOC1    (16H HWIN 0 write)

        (16H HWIN 15 read)

0

select PWM/

1

external interrupt ACH7/

2

Timer1 overflow interrupt enable/

3

Timer2 overflow interrupt enable/

4

HSO.4 output enable/

5

select TXD/

6

HSO.5 output enable/

7

HSI interrupt

FIFO full/

IOS1 (16H HWIN 0 read)

(16H HWIN 15 write)

0

software TIMER0 expired

1

software TIMER1 expired

2

software TIMER2 expired

3

software TIMER3 expired

4

TIMER2 has overflow

5

TIMER1 has overflow

6

HSI FIFO is full

7

HSI holding register data available

bit 0-5 are cleared when read

IOC2 (0BH HWIN 0 write)

(0BH HWIN 15 read)

0

enbale fast increment of T2

1

enable T2 as up/down counter

2

enable/2 prescaler on PWM

3

enable 80C196KC A/D modes

4

A/D clock prescaler diable

5

T2 alternate interrupt 7FFFH->8000H

6

enable locked CAM enters

7

clear enter CAM*

* this bit always reads as 1

IOS2 (17H HWIN 0 read)

(17H HWIN 15 write)

indicated which HSO event occurred

0

HSO.0

1

HSO.1

2

HSO.2

3

HSO.3

4

HSO.4

5

HSO.5

6

T2RESET

7

start A/D

IOS2 is cleared when read

IOC3 (0CH HWIN 1 read/write)

0

Timer2 clock internal/

1

RSV*

2

PWM 1 enable/

3

PWM 2 enable/

4

RSV*

5

RSV*

6

RSV*

7

TSV*

RSV* bit must be writen as 0

4-3. Port ±â´É ¹× ±¸Á¶

80C196KC¿¡´Â P0, P1, P2, P3, P4ÀÇ 5°³ÀÇ IO port°¡ ÀÖÀ¸¸ç, port 0, 1, 2ÀÇ ±¸Á¶´Â ºñ½ÁÇϸç À̵éÀº ¸ðµÎ SFRÀ» ÅëÇؼ­ Á¦¾îÇÑ´Ù. port 1, 2´Â ¾ç¹æÇâ schmitt trigger ÀԷ°ú CMOS level Ãâ·ÂÀ» ÇÒ ¼ö ÀÖ´Ù.

1. Port 0 (P0.0/ACH0 ~ P0.7/ACH7)

port0 Àº ÀÔ·Â Àü¿ë port À̸ç, ditital ÀÔ·ÂÀ» ÇÒ ¼ö ÀÖ°í, ADC¸¦ »ç¿ëÇÒ °æ¿ì analog ÀÔ·ÂÀ¸·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù. ¶Ç P0.7Àº ¿ÜºÎ interrupt request ½ÅÈ£·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù.

digital ÀÔ·ÂÀ¸·Î »ç¿ëÇÒ °æ¿ì¿¡´Â SFRÀÇ PORT0(0EH)À» readÇϸé P0.0~P0.7ÀÇ °ªÀ» ÀÐÀ» ¼ö ÀÖ´Ù.(byte) À̶§ port 0Àº high-impedance ÀÔ·Â ÇÉÀ¸·Î »ç¿ëµÈ´Ù.

ADC·Î »ç¿ëÇÒ °æ¿ì¿¡´Â analog ÀÔ·ÂÀ¸·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù.

IOC1ÀÇ bit1À» "0"À¸·Î Çϸé, P0.7Àº ¿ÜºÎ interrupt request pinÀ¸·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù.

2. Port 1 (P1.0 ~ P1.7)

port1Àº ÀÔ·Â/Ãâ·ÂÀ¸·Î »ç¿ëÇÒ ¼ö ÀÖÀ¸¸ç, ÁØ ¾ç¹æÇ⼺(quasi-bidirectional) portÀÌ´Ù. 196KC¿¡¼­ P1.0~P1.2´Â ÇÑ °¡Áö ±â´É¸¸ ÀÖÁö¸¸, P1.3~P1.7Àº ´Ù¸¥ ±â´ÉÀ» °¡Áö´Â Ư¼ö ±â´É pinÀ¸·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù. port1Àº SFRÀÇ PORT1(0FH)¸¦ ÅëÇؼ­ ÀÐ°í ¾µ ¼ö°¡ ÀÖ´Ù.

port number

direction

´Ù¸¥ ±â´É

P1.3

output

PWM1

P1.4

output

PWM2

P1.5

output

P1.6

output

P1.7

input

 

¿©±â¼­ ÁØ ¾ç¹æÇ⼺ port¶õ, °­ÇÑ "L"À» Ãâ·ÂÇÏ°í, ¾àÇÑ "H"¸¦ Ãâ·ÂÇÏ´Â port¸¦ ¸»ÇÑ´Ù. ÀÌ ¾àÇÑ "H"´Â ¿ÜºÎ¿¡¼­ °­Á¦ÀûÀ¸·Î "L"·Î ¶³¾î¶ß¸± ¼ö°¡ ÀÖ´Ù.

¶Ç ÀÌ port¸¦ ÀÔ·ÂÀ¸·Î »ç¿ëÇÒ °æ¿ì, °¢ port¿¡ "0"À» ½á ³ÖÀº »óÅ¿¡¼­ ÀÔ·ÂÀ»Çϸé, ÇöÀç port pin »óÅ´ "0"À» À¯ÁöÇÏ°í Àֱ⠶§¹®¿¡ ÀÔ·Â ½ÅÈ£¿¡ °ü°è¾øÀÌ "0"¸¸ readµÈ´Ù. µû¶ó¼­ ÀÔ·ÂÀ¸·Î »ç¿ëÇϱâ Àü¿¡ ¹Ýµå½Ã port¿¡ "1"À» writeÇÏ°í Àоî¾ß ÇÑ´Ù.

3. Port 2 (P2.0 ~ P2.7)

port2´Â ¿©·¯ ±â´ÉÀ» °¡Áø ÀÔ·Â/Ãâ·Â port·Î »ç¿ëÇÒ ¼ö ÀÖÁö¸¸, P2.6°ú P2.7¸¸ÀÌ ÁØ ¾ç¹æÇ⼺À» °®°í ÀÖ´Ù. ÀϹÝÀûÀ¸·Î ÀÌ port´Â Ưº°ÇÑ ±â´ÉÀ» À§Çؼ­ »ç¿ëµÈ´Ù. ¶Ç ÀÌ ¶§ ƯÁ¤ ±â´ÉÀ» »ç¿ëÇϱâ À§Çؼ­´Â ÇØ´çµÇ´Â SFRÀÇ ÇØ´ç bit¸¦ control ÇؾßÇÑ´Ù. port2´Â SFRÀÇ PORT2(10H)¸¦ ÅëÇؼ­ accessÇÒ ¼ö ÀÖ´Ù.

port number

direction

´Ù¸¥ ±â´É

P2.0

output

TXD

P2.1

input

RXD

P2.2

input

EXINT

P2.3

input

T2CLK

P2.4

input

T2RST

P2.6

input

T2_U/D

P2.7

input

T2_CAPTURE

 

4. Port 3, 4

port´Â open drain ÀÔ/Ãâ·Â port·Î¼­, 196¿¡¼­ memory mapped IO port·Î »ç¿ëÇÑ´Ù. Áï, port0,. 1, 2¿Í °°ÀÌ SFRÀ» ÅëÇؼ­ accessÇÒ ¼ö°¡ ¾ø´Ù. ¶Ç ÀÌ portµéÀº address/data bus·Î »ç¿ëµÇ±â ¶§¹®¿¡, º¸Åë ÀÏ¹Ý port·Î »ç¿ëÇÏÁö ¾Ê´Â´Ù. port3°ú 4´Â address 1FFEH, 1FFFH·Î ÇÒ´çµÇ¾î ÀÖ´Ù.

            

          Âü°í : http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, µ¿¾Æ¸® °­ÀÇ  

                           Âü°í ¼­Àû : Micro controller 80196 ±âÃʺÎÅÍ ÀÀ¿ë±îÁö - Â÷¿µ¹è Àú


 

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