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2. 196À» ¹è¿öº¸ÀÚ

 

II. 196 pin ±â´É ¹× bus cycle, board design

II-I. 80C196KCÀÇ ÇÉ ±â´É  

1. VCC : main power(5V)

2. VSS : digital ground

3. VREF : Reference voltage for the ADC, +5V, ADC¿¡ °ø±ÞµÇ´Â analog Àü¿øÀ¸·Î, port 0¿¡¼­ logicÀ» readÇϴµ¥ »ç¿ëµÇ¹Ç·Î, port0À» ADC ÀÔ·ÂÀ¸·Î »ç¿ëÇÏ´ø, digital ÀÔ·ÂÀ¸·Î »ç¿ëÇÏ´ø°¡¿¡ °ü°è¾øÀÌ ¹Ýµå½Ã Àü¿ø¿¡ ¿¬°áÇØ¾ß ÇÑ´Ù.

4. ANGND : Analog ground, ADC¸¦ À§ÇÑ analog ±âÁØ Àü¿øÀÌ´Ù. VSS¿Í °°Àº ÀüÀ§°¡ µÇ¾î¾ß ÇÑ´Ù. ÇÑÆí, ÀÌ Àü¿øÀ» digital ground¿Í ¿¬°áÇÒ ¶§¿¡´Â digital noise°¡ analog ground¿¡ ¿µÇâÀ» ÁÖÁö ¾Êµµ·Ï ÇØ¾ß ÇÑ´Ù. Áï, analog GND¿Í digital GND´Â point-to-point·Î ¿¬°áÇÏ´Â °ÍÀÌ ÁÁ´Ù.

5. Vpp : peak to peak voltage,

¨ç power down ȸ·Î¿¡¼­ returnÇϱâ À§ÇÑ timing pin, 1uF capacitor¿Í Vss, 1M§Ù ÀúÇ×°ú Vcc¿¡ ¿¬°áÇÑ´Ù.

¨è 87C196KC¿¡ ³»ÀåµÇ¾î ÀÖ´Â EP-ROMÀ» writeÇÏ´Â °æ¿ì¿¡ »ç¿ëÇÑ´Ù. ÀÌ ±â´ÉÀ» »ç¿ëÇÏÁö ¾Ê´Â´Ù¸é, Vcc¿¡ ¿¬°áÇÑ´Ù.

6. XTAL1 : ³»ºÎ clock ¹ß»ý±â¿Í oscillator inverterÀÇ ÀÔ·Â

7. XTAL2 : oscillator inverterÀÇ Ãâ·Â. XTAL1°ú XTAL2´Â ³»ºÎ oscillator°¡ crystalÀ» ¿¬°áÇÏ¿© »ç¿ëÇÑ´Ù. ÀÌ´Â reference ȸ·Î¸¦ ÂüÁ¶ÇÏ¸é µÈ´Ù.

 

 8. CLKOUT : Clock out, ³»ºÎ clock oscillatorÀÇ Ãâ·Â. oscillator frequencyÀÇ 1/2(duty 50%)ÀÇ frequency°¡ Ãâ·ÂµÈ´Ù.

 9. : reset ÀÔ·Â, open drain Ãâ·Â, active Low, ÃÖ¼Ò 16 state µ¿¾È logic "L"ÀÌ ÀԷµǾî¾ß Çϸç, reset sequence´Â ´ÙÀ½°ú °°´Ù.

  ¨ç clock up-edge¿¡¼­ clkout°ú ´Ù½Ã µ¿±â(synchronize)µÇ¾î, 10 stateµ¿¾È PSW clear,

  ¨è 2018H¿¡¼­ byte¸¦ Àо CCR(Chip Configuration Register)¿¡ load

  ¨é 2080H·Î jumpÇؼ­ programÀ» ½ÃÀÛÇÑ´Ù. ÀÌ ¶§ CPU ³»ºÎÀÇ SFR°ú ¿ÜºÎ pinµéÀº ƯÁ¤ °ªÀ¸·Î ÃʱâÈ­µÇ´Âµ¥, 80C196KCÀÇ Reset status´Â ´ÙÀ½°ú °°´Ù.

10. NMI(Non Maskable Interrupt) : NMI ÀÔ·Â, up-edge¿¡¼­ sampleµÈ´Ù. NMI ISR(Interrupt Service Routine) 203EH·Î jumpÇÑ´Ù.

11. INST(Instruction) : Ãâ·Â, active High, CPU°¡ ÇöÀç instructionÀ» °¡Á®¿À°í ÀÖ´Ù´Â °ÍÀ» Ç¥½ÃÇϱâ À§ÇÑ Ãâ·Â ½ÅÈ£ÀÌ´Ù.

¨ç ¿ÜºÎ memory¿¡¼­ OP code¸¦ fetchÇÏ´Â µ¿¾È "H"°¡ Ãâ·ÂµÈ´Ù. resetÈÄ¿¡ 2080H¿¡ ÀÖ´Â OP code¸¦ fetchÇÏ´Â µ¿¾È¿¡µµ "H"°¡ µÈ´Ù.

¨è reset ÈÄ 2018H¿¡ ÀÖ´Â memory¸¦ readÇؼ­ CCR¿¡ ÀúÀåÇÒ ¶§, 2018HÀÇ ³»¿ëÀº dataÀ̹ǷÎ, ÀÌ °æ¿ì "L"°¡ Ãâ·ÂµÈ´Ù.

¨é IVT(Interrupt Vector Table)À» readÇÒ °æ¿ì¿¡µµ dataÀ̱⠶§¹®¿¡ "L"°¡ Ãâ·ÂµÈ´Ù.

¨ê »ó¼ö³ª º¯¼ö¸¦ readÇÒ ¶§¿¡µµ "L"°¡ Ãâ·ÂµÈ´Ù.

** INST´Â BUS cycleµ¿¾È À¯È¿Çϸç, ´ÜÁö ¿ÜºÎ memory¸¦ accessÇÏ´Â µ¿¾È¿¡¸¸ µ¿ÀÛÇÑ´Ù.

* CCB (Chip Configuration Byte)

80C196KC´Â ResetÀÌ µÇ¸é, ¸Ç óÀ½ 2018HÀÇ CCBÀÇ ³»¿ëÀ» readÇؼ­ CPU ³»ºÎÀÇ CCR(Chip Configuration Register)¿¡ ÀúÀåÇÑ´Ù. CCB´Â chipÀÇ µ¿ÀÛ¿¡ °üÇÑ ±âº»ÀûÀÎ ¼³Á¤ ³»¿ëÀ» °¡Áö°í ÀÖ°Ô µÇ´Âµ¥ ÀÌ´Â ´ÙÀ½°ú °°´Ù.

                  

12. (External Enable) : ÀÔ·Â, ¿ÜºÎ/³»ºÎ ·Ò ¼±Åÿ¡ »ç¿ëµÈ´Ù.

¨ç =H À̸é, 87C196KCÀÏ ¶§ 2000H~5FFFH´Â ³»ºÎ ROM/EP-ROMÀÌ ¼±ÅõȴÙ.

¨è =L À̸é, ¿ÜºÎ ROMÀÌ ¼±ÅõȴÙ. 80C196KC¸¦ »ç¿ëÇÏ´Â °æ¿ì ÀÌ ÇÉÀ» Low·Î ÇؾßÇÑ´Ù.

13. BUSWIDTH : ÀÔ·Â, 8/16bit external data bus width ¼±Åÿ¡ »ç¿ëÇÑ´Ù.

¨ç CCRÀÇ bit 1ÀÌ "1"À̸é, bus cycleµ¿¾È ÀÌ pinÀÇ »óÅ°¡ bus width¸¦ °áÁ¤ÇÑ´Ù. BUSWIDTH=1À̸é 16bit, 0À̸é 8bit bus°¡ µÈ´Ù.

¨è CCRÀÇ bit 1ÀÌ "0"À̸é, BUSWIDTH pin¿¡ °ü°è¾øÀÌ Ç×»ó 8bit bus°¡ µÈ´Ù.

14. ALE/ (Address Latch Enable/Address Valid) : Ãâ·Â, CCR·Î ALE¶Ç´Â ¸¦ ¼±ÅÃÇϸç,      Address/Data bus¿¡¼­ address¸¦ latchÇϱâ À§ÇÑ ½ÅÈ£·Î »ç¿ëµÈ´Ù.

CCRÀÇ bit 3ÀÌ "1"À̸é ALE·Î »ç¿ë, "0"ÀÌ¸é ·Î »ç¿ë

** ALE/ ´Â ´ÜÁö ¿ÜºÎ memory¸¦ accessÇÏ´Â µ¿¾È µ¿ÀÛÇÑ´Ù.

15./ (Read) : Ãâ·Â, active "L", ¿ÜºÎ memory¿¡¼­ data¸¦ Àбâ À§Çؼ­ »ç¿ëÇÏ´Â ½ÅÈ£ÀÌ´Ù.

16. / (Write/Write Low) : Ãâ·Â, active "L", CCR¿¡¼­ / ¼±ÅÃ

¨ç CCRÀÇ bit2°¡ "1"ÀÎ °æ¿ì ·Î »ç¿ëÇÏ¸ç ¿ÜºÎ memory¿¡ data¸¦ writeÇÒ °æ¿ì »ç¿ëÇÑ´Ù. ÀÌ ¶§¿¡´Â ¿ÜºÎ¿¡¼­ /¿Í À» Á¶ÇÕÇÏ¿© /¸¦ ¸¸µé¾î¼­ »ç¿ëÇØ¾ß ÇÑ´Ù.

¨è CCRÀÇ bit2°¡ "0"ÀÎ °æ¿ì ·Î »ç¿ëÇÒ ¼ö ÀÖÀ¸¸ç ¿ÜºÎ memory¿¡ ¦¼ö address·Î data¸¦ writeÇÒ ¶§ »ç¿ëÇÑ´Ù.

** / µµ ¿ÜºÎ memory¸¦ accessÇÏ´Â µ¿¾È¿¡ µ¿ÀÛÇÑ´Ù.

17. / (Bus High Enable/Write High) : Ãâ·Â, CCR¿¡¼­ ¼±ÅÃ

¨ç CCRÀÇ bit2°¡ "1"ÀÎ °æ¿ì ½ÅÈ£·Î »ç¿ëÇϸç, ´Â »óÀ§ data bus(D15~D8), Address bus A0´Â ÇÏÀ§ data bus(D7~D0)ÀÇ µ¿ÀÛÀ» Á¦¾îÇÑ´Ù. Áï,

BHE#

A0

D15~D8

D7~D0


1

0

No

active

even address(byte)

0

1

active

No

odd address(byte)

0

0

active

active

even address(byte)

 

¨è CCRÀÇ bit2°¡ "0"ÀÎ °æ¿ì ·Î »ç¿ëµÇ¸ç, odd address·Î data¸¦ writeÇÒ °æ¿ì »ç¿ëÇÑ´Ù./ ´Â 16bit data bus¸¦ »ç¿ëÇÏ¿© writeÇÒ °æ¿ì¿¡ »ç¿ëµÈ´Ù.

18. READY : ÀÔ·Â, active "L", ¿ÜºÎ memory cycleÀ» ±æ°Ô Çϱâ À§Çؼ­ »ç¿ëÇÑ´Ù. Áï, ¿ÜºÎÀÇ ´À¸° IO³ª memory¸¦ accessÇÒ ¶§ bus cycleÀ» ´À¸®°Ô Çϴµ¥ »ç¿ëÇÑ´Ù.

READY="H"À̸é CPU´Â wait state¾øÀÌ bus cycleÀ» ÁøÇàÇÏ°í, "L"À̸é memory controller´Â wait state°¡ µÈ´Ù. ¿ÜºÎ memory¸¦ »ç¿ëÇÏÁö ¾ÊÀ» ¶§¿¡´Â READY½ÅÈ£´Â »ç¿ëÇÏÁö ¾ÊÀ¸¸ç, bus cycle¿¡ »ðÀԵǴ wait ¼ö´Â READY ½ÅÈ£¸¦ ÀÌ¿ëÇÏÁö ¾Ê°í, CCRÀÇ bit 4,5¸¦ ÀÌ¿ëÇÒ ¼öµµ ÀÖ´Ù.

19. HSI(High Speed Input) : °í¼Ó ÀÔ·Â pin, 4°³ÀÇ HSI(HSI.0, HSI.1, HSI.2, HSI.3)¸¦ »ç¿ëÇÒ ¼ö ÀÖ°í, HSI.2¿Í HSI.3Àº HSO¿Í ÇÔ²² »ç¿ëÇÒ ¼ö ÀÖ´Ù.

20. HSO(High Speed Output) : °í¼Ó Ãâ·Â pin, 6°³ÀÇ HSO(HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, HSO.5)¸¦ »ç¿ëÇÒ ¼ö ÀÖÀ¸¸ç, HSO.4¿Í HSO.5´Â HSI¿Í °°ÀÌ »ç¿ëÇÒ ¼ö ÀÖ´Ù.

21. port 0(P0.0/ACH0~P0.7/ACH7) : 8bit high-Z input port, ÀÌ port´Â digital ¶Ç´Â analog ½ÅÈ£¸¦ ÀÔ·Â(ADC)ÇÏ´Â µ¥¿¡ »ç¿ëµÈ´Ù.

¨ç P0.0/ACH0~P0.7/ACH7 : digital/analog input

¨è P0.4/ACH4/PMODE0~P0.7/ACH7/PMODE3 : digital/analog input/87C196KCÀÇ EP-ROM write¿¡¼­ write mode °áÁ¤

¨é P0.7Àº EXINT1(external interrupt 1)·Î »ç¿ëÇÒ ¼ö ÀÖ´Ù.

22. port 1(P1.0~P1.7) : 8bit ÁØ ¾ç¹æÇâ(quasi-bidirectional) port, ¹ü¿ë IO port·Î »ç¿ëÇÑ´Ù.

¨ç P1.0~P1.2 : IO port·Î »ç¿ëÇÑ´Ù.

¨è P1.3/PWM1, P1.4/PWM2 : IO port ¹× PWM(Pulse Width Modulation)·Î »ç¿ëÇÑ´Ù.

¨é P1.5/ , P1.6/ , P1.7/: IO port ¹× DMA(Direct Memory Access)¿¡¼­ »ç¿ëÇÑ´Ù.

23. Port 2 : 8bit ´Ù±â´É Æ÷Æ® : port2´Â ¸ðµÎ ´Ù¸¥ ±â´Éµé°ú multiplexµÇ¾î ÀÖ´Ù.

¨ç ¹ü¿ë IO port·Î »ç¿ë

¨è multiplexµÈ ±â´Éµé

´Ù¸¥ ±â´É

¹æÇâ

±â´É

SFR

P2.0/TXD

output

Transmit data(Serial)

IOC1.5

P2.1/RXD

input

Receive data(Serial)

SPCON.3

P2.2/EXINT

input

external interrupt input

IOC1.1

P2.3/T2CLK

input

Timer 2 clock & baud

IOC0.7

P2.4/T2RST

input

Timer 2 Reset

IOC0.5

P2.5/PWM0

output

PWM output

IOC1.0

P2.6/T2UP-DN

bi-directional

Timer 2 up/down select

IOC2.1

P2.7/T2CAP

bi-directional

Timer 2 capture

N/A

 

¨é ¶Ç 87C196KCÀÇ °æ¿ì EP-ROM writeÀÇ Á¦¾î ½ÅÈ£·Î »ç¿ëµÈ´Ù.

24. Port 3/4 : 8bit bi-directional port(open drains), ÀÌ portµéÀº ¿ÜºÎ memory access½Ã¿¡ address/data bus·Î »ç¿ëÇÑ´Ù.(³»ºÎ¿¡ °­ÇÑ pullup ÀúÇ×À» °¡Áö°í ÀÖ´Ù.)

¨ç AD0/P3.0~AD7/P3.7 : address/data bus AD0~AD7

¨è AD8/P4.0~AD15/P4.7 : address/data bus AD8~AD15

Âü°í : http://www.postech.ac.kr/group/poweron/ - lectures/Micro processor, controller, µ¿¾Æ¸® °­ÀÇ

                        Âü°í ¼­Àû : Micro controller 80196 ±âÃʺÎÅÍ ÀÀ¿ë±îÁö - Â÷¿µ¹è Àú



 

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